Optimization of Vertical Double-Diffused Metal-Oxide Semiconductor (VDMOS) Power Transistor Structure for Use in High Frequencies and Medical Devices
Keywords:
VDMOS transistor, UIS implant, electrocardiograph machine, noise, high frequencyAbstract
Power transistors, such as the vertical, double-diffused, metal-oxide semiconductor (VDMOS), are used extensively in the amplifier circuits of medical devices. The aim of this research was to construct a VDMOS power transistor with an optimized structure to enhance the operation of medical devices. First, boron was implanted in silicon by implanting unclamped inductive switching (UIS) and a Faraday shield. The Faraday shield was implanted in order to replace the gate-field parasitic capacitor on the entry part of the device. Also, implanting the UIS was used in order to decrease the effect of parasitic bipolar junction transistor (BJT) of the VDMOS power transistor. The research tool used in this study was Silvaco software. By decreasing the transistor entry resistance in the optimized VDMOS structure, power losses and noise at the entry of the transistor were decreased, and, by increasing the breakdown voltage, the lifetime of the VDMOS transistor lifetime was increased, which resulted in increasing drain flow and decreasing Ron. This consequently resulted in enhancing the operation of high-frequency medical devices that use transistors, such as Radio Frequency (RF) and electrocardiograph machines.
References
Ghamati M. Low-noise low-power MOSFET only electrocardiogram amplifier. Conference Publications ofElectrical Engineering (ICEE). 2013;13767968 (3):1-52.Cai WZ, Gogoi BS, Loechelt GH. TCad Analysis of a Vertical RF Power Transistor. Conference of SanDiego USA. 2009; 978-1-4244-3947-8(5):249-523.Zoaeter M, Beydoun B, Hajjar M, Debs M, Charles J-P. Analisis and Simulation of Functional StressDegradation on VDMOS Power Transistors. J of Active and Passive Elec. 2002; 25(8):215–223. DOI:http://dx.doi.org/10.1080/088275102135004.Ren M, Hong Z. A. Novel planar vertical double-diffused metal-oxide semiconductor field-effect transistorwith in homogeneous floating islands Chin. IEEE electron dev lett. 2011;20(12): 7-125.Zhaohuan T, Gangyi HU. Novel structure for improving the SEGR of a VDMOS. Journal ofSemiconductors. 2012;33(4):982-4.DOI:http://dx.doi.org/10.1088/1674-4926/33/4/0440026.Roig J, Mouhoubi S. New VDMOS Structure with Discontinuous Thick Inter-Body Oxide to Reduce Gate-to-Drain Charge Process Development & Integration. journal of Corporate R&D ONSemiconductor. 2011;36(4):25-327.Ueda D, Takagi H.A new vertical double diffused MOSFET—the self-aligned terraced-gate MOSFET.IEEE Trans On Elec Devices. 1984; 31(4):416–20. DOI:http://dx.doi.org/10.1109/T-ED.1984.215438.Yih C, Cheng S.A new approach to simulating n-MOSFET gate current degradation by including hot-electron induced oxide damage. IEEE Transaction on Electron Devices.1998;45(11):2343–8. DOI:http://dx.doi.org/10.1109/16.726653
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